Tag Archives: power

New paper published: “Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors”

tlab PhD student Byron Gregg presented both a paper and a poster on “Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors” at “The 15th International Green and Sustainable Computing Conference,” Austin, TX, 2024.

IGSCC proceedings: https://www.computer.org/csdl/proceedings/igsc/2024/22gEnJUWwMg 

Citation:

B. Gregg and C. Teuscher, “Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors,” 2024 IEEE 15th International Green and Sustainable Computing Conference (IGSC), Austin, TX, USA, 2024, pp. 135-141, doi: 10.1109/IGSC64514.2024.00033.

Abstract:

Although highly energy efficient, adiabatic and reversible systems suffer from performance drawbacks inherent to the physical operations that make them so efficient. Superscalar processors provide high performance through out-of-order speculative work of which an effective branch predictor is a key component in those performance gains. In the context of reversibility, a branch predictor is a design focal point because any fully reversible system must also be able to predict branch outcomes when in reverse mode. Taking advantage of Temporal Streaming techniques, this paper introduces several reversible branch predictor implementations which enable reversible and out-of-order instruction execution. These first-of-their-kind designs allow for a superscalar architecture that would maintain both a high level of performance and a high level of energy efficiency with the ability to un-compute obsolete data stored in memory. Testing our designs using the SimpleScalar out-of-order simulator, we estimate possible additional savings of 24 fJ per MB of data recovered at room temperature and at reverse prediction rates 2.27% higher than the forward. This work opens new avenues for designing and developing what we are calling Fully Adiabatic, Reversible, and Superscalar (FARS) Processor Architectures and is the first of many adaptations of conventional superscalar components to a reversible system.

Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture

Walt Woods, Ph. D. candidate, and Christof Teuscher, Electrical and Computer Engineering Faculty, co-authored “Fast and Accurate Sparse Coding of Visual Stimuli with a Simple, Ultra-Low-Energy Spiking Architecture,” published in IEEE Transactions on Neural Networks and Learning Systems.

The V1 visual layer of mammalian brains has been identified as performing Sparse Coding (SC) to help the rest of the brain process imagery received from the eyes.  Sparse coding is the compression of input stimulus in such a way that retains key details while saving energy by not transmitting irrelevant details.  In this work, Woods et al. proposed a new architecture named the Simple Spiking Locally Competitive Algorithm (SSLCA).  The proposed SSLCA uses spiking signals, inspired by the spiking signals used in biological brains, to take visual information and re-encode that information in a sparse format for easier processing.  The architecture was enabled through the use of memristors, next-generation nanodevices with dynamic resistances. Using these devices to weight and transmit information between the image input and the resulting sparse code, the SSLCA consumes only 1% of the energy and processes images at a rate 21 times higher than previously proposed sparse coding architectures.  Even though memristors are noisy devices that do not produce clean signals, the architecture was shown to be resistant to write variances of up to 27% and read variances of up to 40%. Woods et al. also researched the combination of such a sparse coding device with a state-of-the-art deep neural network for image processing, showing that, like the V1 cortex, the SSLCA can compress visual information efficiently while retaining necessary details for good classification performance.  Sparse coding architectures such as the proposed SSLCA could be used to greatly reduce communication bandwidth between visual sensors and other processing algorithms, such as deep learning networks.
Full paper: https://doi.org/10.1109/TNNLS.2018.2878002