Session I
Kaushik Roy
Re-engineering computing with spike based learning: algorithms to devices
Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional “von-Neumann” architectures are several orders of magnitude more area and power expensive than the biological brain. Hence, we need fundamentally new approaches to sustain the exponential growth in performance at high energy-efficiency. Exploring the new paradigm of computing necessitates a multi-disciplinary approach: exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the neuronal and synaptic operations. In this talk, I will present our recent work on spike-based learning (rate-coded inputs) to achieve high energy efficiency with accuracy comparable to that of standard analog deep-learning techniques. Input coding from DVS cameras have been to develop energy efficient hybrid SNN/ANN networks for optical flows, gesture recognition, and language translation. Additionally, we propose probabilistic neural and synaptic computing platforms that can leverage the underlying stochastic device physics of spin-devices. System-level simulations indicate ~100x improvement in energy consumption for such spintronic implementations over a corresponding CMOS implementation across different computing workloads. Complementary to the above device efforts, we have explored different local/global learning algorithms including stochastic learning with one-bit synapses that greatly reduces the storage/bandwidth requirement while maintaining competitive accuracy, and adaptive online learning that efficiently utilizes the limited memory and resource constraints to learn new information without catastrophically forgetting already learnt data.
Yiran Chen
Spiking Neuromorphic System Design Through Abstraction: Circuit and Algorithm Techniques in Brain-inspired Computing
Priya Panda
Toward Scalable, Efficient, and Accurate Deep Spiking Neural Networks
Spiking Neural Networks (SNNs) offer an energy-efficient alternative for implementing deep learning applications. In recent years, there have been several proposals focused on supervised (conversion, spike-based gradient descent) and unsupervised (spike timing dependent plasticity) training methods to improve the accuracy of SNNs on large-scale tasks. However, each of these methods suffer from scalability, latency, and accuracy limitations. We will delve into the details of these limitations with SNNs. Further, we will talk about certain algorithmic techniques of modifying the SNN configuration with backward residual connections, stochastic softmax, and hybrid artificial-and-spiking neuronal activations to improve the learning ability of the training methodologies to yield competitive accuracy, while, yielding large efficiency gains over their artificial counterparts.
Session II
Rajit Manohar
Self-Timed Neuromorphic Systems
Neuromorphic systems aim to use electronics to replicate human
intelligence. Mimicking biological systems that operate in
continuous-time requires a combination of continuous-time analog and digital electronics. Many past and recent neuromorphic systems use self-timed digital electronics to achieve energy-efficient operation. We will discuss some of the uses of self-timed logic in the design of the TrueNorth and Braindrop neuromorphic systems, and some ongoing work to make this design methodology more accessible to researchers in this space.
Jae-sun Seo
Fully Spike-based Architecture with Front-end Dynamic Vision Sensor and Back-end Spiking Neural Network
Spiking neural networks (SNN) mimic the operations in biological nervous systems. By exploiting event-driven computation and data communication, SNNs can achieve very low power consumption. However, two important issues have persisted: (1) directly training SNNs have not resulted in competitive inference accuracy; (2) non-spike inputs (e.g. natural images) need to be converted to a train of spikes, which results in long latency.
To exploit event-driven end-to-end operations, we propose integrating front-end sensors that are spike-based such as dynamic vision sensors (DVS) and back-end SNNs for object/motion detection. We also present a back-propagation based training algorithm that can directly train SNNs with continuous input spikes from DVS output. Based on this, we devised a fully spike-based architecture, and implemented neuromorphic hardware in 28nm CMOS that exploits the spike sparsity and demonstrates high inference accuracy for small-scale networks. We will also discuss on-going work on enhanced fully spike-based architecture for large-scale networks.
Yu Cao
Continual learning at the edge: Neural inspiration, model robustness and hardware efficiency
With the proliferation of sensors and edge devices, there is a growing demand for an intelligent system to continually monitor the environment and adaptively expand the knowledge in real time, with high accuracy and high computation efficiency. In this talk, we will start from the latest biological understanding in this field, such as memory consolidation and knowledge inheritance. Then we will present the state-of-the-art approaches from algorithm and hardware perspectives. In particular, we emphasize the importance of both knowledge inheritance and model adaptation in continual learning, which effectively reduces catastrophic forgetting by 10X on representative datasets. Moreover, we develop an FPGA prototype for online learning, achieving 5X reduction in training latency. Finally, we will explore a hybrid memory architecture for future learning at the edge.
Gert Cauwenberghs
Towards Efficient Neuromorphic Learning and Inference at Scale
The human brain offers an existence proof of general intelligence realized by hierarchical assemblies of massively parallel, yet imprecise and slow compute elements that operate near fundamental limits of noise and energy efficiency. We continue to be guided by biology in pursuing their instantiations in neuromorphic very large-scale integrated electronic circuits. These neuromorphic realizations have evolved from highly specialized, task-specific compute-in-memory neural and synaptic crossbar array architectures that operate near the efficiency of synaptic transmission in the human brain, to large tiles of such neurosynaptic cores assembled into hierarchically interconnected networks for general-purpose learning and inference. By combining extreme efficiency of local interconnects (grey matter) with great flexibility and sparsity in global interconnects (white matter), these assemblies are capable of realizing a wide class of deeply layered and recurrent neural architectures with embedded local plasticity for on-line learning, at a fraction of the computational and energy cost of GPGPU implementations. A proof-of-concept reconfigurable memristive neurosynaptic core integrated in 130nm CMOS-RRAM demonstrates a record 74 TMACS/W efficiency in visual pattern classification and reconstruction.
Session III
Abhronil Sengupta
Spintronics Enabled Neuromorphic Computing: Hardware-Algorithm Co-Design
While research in designing brain-inspired algorithms have attained a stage where such Artificial Intelligence platforms are being able to outperform humans at several cognitive tasks, an often-unnoticed cost is the huge computational expenses required for running these algorithms in hardware. Bridging the computational efficiency gap necessitates the exploration of devices, circuits and algorithms that provide a better match to the computational primitives of biological processing – neurons and synapses, and which require a significant rethinking of traditional von-Neumann based computing. Recent experiments in spintronic technologies are revealing immense possibilities of implementing a plethora of neural and synaptic functionalities by single spintronic device structures that can be operated at very low terminal voltages. Leveraging insights from such experiments, we present a multi-disciplinary perspective across the entire stack of devices, circuits and systems to envision the design of an “All-Spin” neuromorphic processor enabled with on-chip learning functionalities that can potentially achieve two to three orders of magnitude energy improvement in comparison to state-of-the-art CMOS implementations. We also discuss recent innovations at the algorithm front on exploring event-driven Spiking Neural Networks for large-scale machine learning tasks. Such neuromorphic systems can potentially provide significantly lower computational overhead in contrast to standard deep learning platforms, especially in sparse, event-driven application domains with temporal information processing. I will conclude the presentation by providing the prospects of enabling end-to-end cognitive intelligence across the computing stack that combines knowledge from devices and circuits to machine learning and computational neuroscience.
Emre Neftci
Data and Power Efficient Intelligence with Neuromorphic Hardware
The potential of machine learning and deep learning to advance artificial intelligence is driving a quest to build dedicated computers, such as neuromorphic hardware that emulate the biological processes of the brain. This talk will present interdisciplinary approaches anchored in machine learning theory and computational neurosciences that can enable neuromorphic technologies for real-world, human-centric tasks. In particular, I’ll discuss the following related challenges and their possible solutions:
(1) The models and tools of deep learning can be transferred to neuromorphic hardware, but its architectural constraints call for novel, continual and local learning algorithms;
(2) Neuromorphic technologies have potential advantages over conventional computers on tasks where real-time adaptability, autonomy or energy efficiency are necessary, but applications and benchmarks benefiting from these qualities are not yet identified;
(3) Challenges in memory technologies, compounded by a tradition of bottom-up approaches in the field and the lack of large-scale simulation environments block the road to major breakthroughs. Our recent work addresses these challenges and pave the way towards building brain-inspired computers and algorithms on solid mathematical foundations. In turn, these solutions articulate the roadmap towards Tensorflow-like programming of neuromorphic hardware.
Joshua Yang
Resistive and capacitive crossbar arrays for neuromorphic computing
Memristive devices have become a promising candidate for neuromorphic computing due to their attractive properties. The computing can be implemented on a Resistive Neural Network (ResNN) with memristor synapses and neurons or a Capacitive Neural Network (CapNN) with memcapacitor synapses and neurons.
For ResNNs as computing accelerators, we have built a dot-product engine based on a 128 x 64 1T1R crossbar array using traditional non-volatile memristors with 64 stable analog resistance levels. With such computation accelerators, we have demonstrated efficient inference and learning with traditional Machine Learning algorithms, which is expected to significantly improve the speed and energy efficiency of neural networks.
For ResNNs beyond accelerator applications, we developed diffusive memristors with diffusion dynamics that is critical for neuromorphic functions. Based on the diffusive memristors, we have further developed artificial synapses and neuronsto more faithfully emulate their bio-counterparts. We then integrated these artificial synapses and neurons into a small neural network, with which pattern classification and unsupervised learning have been demonstrated.
For CapNNs, we have developed pseudo-memcapacitive devices based on the diffusive memristors. Capacitive synapses and neurons enabled by these memcapacitive devices have been developed and used to form a fully integrated CapNN, which can implement spiking signal classification and Hebbian-like learning.
Session IV
John Paul Strachan
Pushing the benefits of neuromorphic computing toward broad applications and broad adoption
While neuromorphic hardware has promise to bring increased energy efficiency for applications across perception, classification, decision-making, and beyond, it is important to consider some of the practical challenges faced by users and customers. As a researcher within industry, I will share some of the challenges that need to be addressed before we see ubiquitous adoption of the current waves of A.I. across industry. In the second part of my talk, I would like to share some of my team’s research in in-memory computing, benefiting from non-volatile memories while co-designing from algorithms to architectures. Beyond the acceleration of deep learning algorithms, we have explored systems built around content-addressable memories, both digital and analog, that enable rapid pattern matching for applications from network security to genomics
Hsinyu Tsai
Analog Memory-based techniques for Accelerating Deep Neural Networks
Deep neural networks (DNNs) are the fundamental building blocks that allowed explosive growth in machine learning sub-fields, such as computer vision and natural language processing. Von Neumann-style information processing systems — in which a “memory” delivers operations and then operands to a dedicated “compute unit” — are the basis of modern computer architectures. As Moore’s Law slowing and Dennard scaling ended, data communication between memory and compute, i.e. the “Von Neumann bottleneck,” now dominates considerations of system throughput and energy consumption, especially for DNN workloads. Non-Von Neumann architectures, such as those that move computation to the edge of memory crossbar arrays, can significantly reduce the cost of data communication. Crossbar arrays of resistive non-volatile memories (NVM) offer a novel solution for deep learning tasks by computing matrix-vector multiplication in analog memory arrays. The highly parallel structure and computation at the location of the data enables fast and energy-efficient multiply accumulate computations, which are the workhorse operations within most deep learning algorithms. In this presentation, we will discuss our Phase-Change Memory (PCM) based analog accelerator implementations for training and inference. In both cases, DNN weights are stored within large device arrays as analog conductances. Software-equivalent accuracy on various datasets has been achieved in a mixed software-hardware demonstration despite the considerable imperfections of existing NVM devices, such as noise and variability. We will discuss the device, circuit and system needs, as well as performance outlook for further technology development.
Narayan Srinivasa
Towards learning systems that understand
AI models today mostly follow the classical model of representation to learn about concepts and but these models lack the ability to understand. We need new models that understand by addressing: how contexts can influence concepts in diverse and unexpected ways, how concepts could combine spontaneously to generate new meaning and how concepts could align spontaneously to generate new meaning. Neuromorphic computing models that exploit both structural and functional aspects of brain like architecture and dynamics may offer a path forward towards building systems that understand.