Category Archives: News

Select a news topic from the list below, then select a news article to read.

NEW COURSE: Hardware for Artificial Intelligence and Machine Learning

More and updated info at Hardware for Artificial Intelligence and Machine Learning

Offered:

Spring 2025

Course description:

Hardware (HW) is the foundation upon which artificial intelligence (AI) and machine learning (ML) systems are built. It provides the necessary computational power, efficiency, and flexibility to drive innovation in these emerging fields. By using HW/SW co-design, students will learn how to use, design, simulate, optimize, and evaluate specialized HW, such as GPUs, TPUs, FPGAs, and neuromorphic chips, for modern AI/ML algorithms. The intersection of HW and AI/ML is a rapidly growing field with significant career opportunities for computer engineers.

Course organization:

  • The course is offered in-person only.
  • There will be no course recordings.
  • The course is organized into 18 lectures. Two of the lectures are dedicated for student presentations (mid-term and final project).

Learning outcomes:

  • Understand the principles and tools for SW/HW co-design.
  • Understand the foundations of neural networks.
  • Understand the foundations of Large Language Models (LLMs).
  • Understand the foundations of specialized hardware for AI/ML, such as GPUs, TPU, FPGAs, and neuromorphic architectures.
  • Capable of mapping algorithms onto hardware.
  • Capable of evaluating HW designs.
  • Capable of optimizing HW designs through co-design for computational power, efficiency, and flexibility.
  • Capable of using modern SW and HW tools for designing and using specialized HW for AI/ML.

Tentative course plan:

General catalog and banner information:

  • Course prefix: ECE
  • Course number: 410/510
  • Catalog course title: Hardware for Artificial Intelligence and Machine Learning
  • Credit hours: 4
  • Grading option: Letter grade
  • Course intended for: Graduate and undergraduate students
  • Instructional method: Lecture
  • Prerequisites (recommendations):
    • Undergraduate: ECE 371 and ECE 351
    • Graduate: ECE 485

More info:

Hardware for Artificial Intelligence and Machine Learning

Call for Artists-in-the-Lab (AiL)

The Artist-in-the-Lab (AiL) program aims at fostering the collaboration between art, science, and technology. Artists will be embedded in the teuscher.:Lab lab at Portland State University where they can engage and interact with scientists and students to gain a deeper understanding of cutting-edge science and technology. More info at https://www.teuscher-lab.com/ail

What computes? What doesn’t?

Dr. Teuscher gave a plenary presentation entitled “Alternative ways of computing What computes, what doesn’t?” at the 9th Annual IEEE International Conference on Rebooting Computing (ICRC), San Diego, CA, Dec 16-17, 2024.

New paper published: “Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors”

tlab PhD student Byron Gregg presented both a paper and a poster on “Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors” at “The 15th International Green and Sustainable Computing Conference,” Austin, TX, 2024.

IGSCC proceedings: https://www.computer.org/csdl/proceedings/igsc/2024/22gEnJUWwMg 

Citation:

B. Gregg and C. Teuscher, “Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors,” 2024 IEEE 15th International Green and Sustainable Computing Conference (IGSC), Austin, TX, USA, 2024, pp. 135-141, doi: 10.1109/IGSC64514.2024.00033.

Abstract:

Although highly energy efficient, adiabatic and reversible systems suffer from performance drawbacks inherent to the physical operations that make them so efficient. Superscalar processors provide high performance through out-of-order speculative work of which an effective branch predictor is a key component in those performance gains. In the context of reversibility, a branch predictor is a design focal point because any fully reversible system must also be able to predict branch outcomes when in reverse mode. Taking advantage of Temporal Streaming techniques, this paper introduces several reversible branch predictor implementations which enable reversible and out-of-order instruction execution. These first-of-their-kind designs allow for a superscalar architecture that would maintain both a high level of performance and a high level of energy efficiency with the ability to un-compute obsolete data stored in memory. Testing our designs using the SimpleScalar out-of-order simulator, we estimate possible additional savings of 24 fJ per MB of data recovered at room temperature and at reverse prediction rates 2.27% higher than the forward. This work opens new avenues for designing and developing what we are calling Fully Adiabatic, Reversible, and Superscalar (FARS) Processor Architectures and is the first of many adaptations of conventional superscalar components to a reversible system.